1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a highly integrated dynamic random access memory (DRAM) that connects to a DRAM controller for a less integrated DRAM.
2. Description of the Related Art
DRAMs have been widely used in computers. In a computer, a DRAM controller controls writing and reading of data to and from the DRAMs. Accordingly, a row or column address output from a DRAM controller should have the same number of address bits as the address input to the DRAM, and the number of address pins of the DRAM controller should match the number of address pins of the DRAM.
Referring to FIG. 1A, a controller 101 for 128 Mb DRAM has twelve address pins 11 to 22, and a 128 Mb DRAM 111 has twelve address pins 51 to 62. Each of the twelve address pins 11 to 22 of controller 101 connects to a corresponding one of the twelve address pins 51 to 62 of 128 Mb DRAM 111. Therefore, when reading from or writing to 128 Mb DRAM 111, controller 101 issues a row address and a column address, each having up to twelve bits A0 to A11 through address pins 11 to 22, and 128 Mb DRAM 111 receives the address bits through address pins 51 to 62.
In contrast, referring to FIG. 1B, controller 101 has twelve address pins 11 to 22 for a 128 Mb DRAM, and a 256 Mb DRAM has thirteen address pins 71 to 83 and requires a row or column address with up to thirteen bits for access of the full address space of DRAM 131. Since the number of address pins 11 to 22 supported by DRAM controller 101 is less than the number of address pins 71 to 83 required by DRAM 131, DRAM controller 101 cannot control DRAM 131.
Referring to FIG. 2, a conventional 256 Mb (64M.times.4 bits) DRAM 201 includes pads 250 to 262, address buffers 270 to 282, a row decoder 211, first and second memory cell arrays 221 and 222, I/O (input/output) line sense amplifiers 231 to 238, and four pairs of I/O lines 100 to 103. A column decoder and associated circuitry that also connect to pads 250 to 262 are not shown but are well known in the art. Similarly, arrays 221 and 222 are simplified to only show column lines associated with columns selected by a column address received via pads 250 to 262.
The most significant row address bit A12 of row address bits A0 to A12 determines which of first and second memory cell arrays 221 and 222 will operate. For example, when the most significant row address bit A12 is logic high, bit A12 enables a row line driver 215 which assert a signal for accessing memory cells coupled to one of word lines WL.sub.0 to WL.sub.n that address bits A0 to A11 select. Bit A12 disables a row line driver 216 from asserting the signal to word lines WL.sub.0 to WL.sub.n in array 222 when row address bit A12 is a logic high. I/O line sense amplifiers 231 to 234 amplify data signals from memory cells on the selected word line and output the data via I/O (input and output) lines 100 to 103.
When the most significant row address bit A12 is logic low, row address bits A0 to A11 select one of word lines WL.sub.0 to WL.sub.n, and bit A12 enables word line driver 216 to assert the access signal from a decoder 213 to the selected word line in second memory cell array 222. Then, I/O line sense amplifiers 235 to 238 amplify data signals from memory cells on the selected word line and output the data via I/O (input and output) lines 100 to 103.
Referring to FIG. 3, a conventional 256 Mb (32M.times.8 bits) DRAM 301 includes pads 350 to 362, address buffers 370 to 382, a row decoder 311, first and second memory cell arrays 321 and 322, sense amplifiers 331 to 346, and pairs of I/O (input and output) lines 100 to 107. 256 Mb (32M.times.8 bits) DRAM 301 has a similar structure and operation to those of 256 Mb (64M.times.4 bits) DRAM 201 of FIG. 2, but accesses eight (instead of four) columns in array 321 or 322 for a read or write. As in FIG. 2, circuitry associated with column decoding is not shown in FIG. 3 but is well known in the art. For the 32M.times.8 memory fewer column address bits (i.e., twelve column address bits) are used rather than thirteen column address bits as in the 64M.times.4 memory. Both 64M.times.4 and 32M.times.8 use thirteen row address bits.
As mentioned above, a controller for 128 Mb DRAM cannot be used with conventional 256 Mb DRAM 201 or 301 of FIGS. 2 and 3 because a conventional 128 MB DRAM controller only provides twelve row address bits and memories 201 and 301 require thirteen row address bits. Accordingly, when memory ICs in a computer are upgraded, the upgraded memory ICs require a new controller. For cost-effective memory IC upgrading, a memory IC that can be operated by a controller for a memory IC having less memory capacity is necessary.